Content addressable memory (CAM) devices, sometimes referred to as “associative memories,” can receive a compare data value (sometimes referred to as a comparand or search key), and compare such a value against a number of stored data values. In most configurations, such an operation can match a compare data value against a very larger number of stored data values (e.g., thousands or millions), essentially simultaneously.
Such rapid compare functions have resulted in CAM devices enjoying wide application in various packet processing hardware devices, such as routers and network switches, to name just two. In a typical packet processing operation, a device can receive a packet. The packet can include a “header” that includes various data fields that indicate how the packet should be processed. The hardware device can use a matching function, provided by a CAM, to compare one or more header fields to stored data values that can indicate how the packet is to be processed.
Many CAM device configurations can include a number of CAM memory cells arranged in a logical fashion (e.g., rows, words, etc.) to store data values for comparison with a search key. Such CAM memory cells typically include a storage circuit for storing one or more bit values as well as a compare circuit, for comparing the stored data value(s) with corresponding portions of a received search key.
CAM devices are typically manufactured in integrated circuit form, as stand alone memory devices, or as some portion of an integrated circuit providing other functions. For many integrated circuit applications, including those that include CAM memory cells, current draw can be an important feature. That is, it is desirable to reduce current draw in an integrated circuit to as great an extent as possible.
To better understand various aspects of the present invention, a conventional CAM device circuit will briefly be described.
FIG. 30 shows an example of an “XY” ternary CAM (TCAM) device 3000 that includes three XY TCAM cells 3002-0 to 3002-2 arranged in parallel with one another between a match line 3004 and a discharge node 3006. Each XY CAM cell (3002-0 to 3002-2) can include two storage circuits (shown by example as 3008-0, 3008-1) and a compare circuit (shown by example as 3010). XY CAM cells (3002-0 to 3002-1) can be configured to execute particular match operations according to values stored and provided by their corresponding storage circuits (e.g., 3008-0 and 3008-1). For example, a configuration X=0, Y=1 can result in a match when an applied compare bit value CD=1, while the opposite configuration (X=0, Y=1) can result in a match when an applied compare bit value CD=0. If both X and Y values are zero, the CAM cell can be in a masked state, and thus match regardless of the compare data value (CD=1 or 0). If both X and Y values are one, the CAM cell can be in an “empty” state, and thus mis-match regardless of the compare data value (CD=1 or 0).
Referring still to FIG. 30, compare operations for the TCAM device 3000 can rely on precharging match line 3004 to a relatively high potential, to create a difference in voltage between the match line 3004 and discharge node 3006. If a bit compare operation for all TCAM cells indicates a match (or mask), the compare circuits (e.g., 3010) can maintain a high impedance, and match line 3004 can remain at a precharge level. However, if any TCAM cell indicates a mis-match, a corresponding compare circuit (e.g., 3010) will create a low impedance path between match line 3004 and discharge node 3006, resulting in the match 3006 line being discharged to a potential lower than the precharge potential.
In the particular example of FIG. 30, each compare circuit (e.g., 3010) can include four n-channel insulated gate field effect transistors N300-N303, with transistors N300 and N302 having source-drain paths in series between match line 3004 and discharge node 3006, while transistors N1 and N3 have source-drain paths in series between match line 3004 and discharge node 3006. Thus, transistors N300/N302 can form one discharge path, while transistors N301/N303 can form another discharge path.
Transistor N300 can receive a first compare data value CD at its gate. Transistor N301 can receive a second compare data value /CD at its gate. Transistor N302 can receive value X at its gate. Transistor N303 can receive value Y at its gate.
In a match operation, each of compare data values CD and /CD can be driven to complementary values, to thereby enable a compare operation within a corresponding compare circuit (e.g., 3010). However, before a match operation, compare data value CD, /CD can all be driven low. This can result in compare circuits (e.g., 3010) of all the TCAM cells (e.g., 3010) having a high enough impedance between match line 3004 and discharge node 3006 to enable match line 3004 to be precharged.
Unfortunately, even with logic low values applied to both transistors N300 and N301, such transistors may still be subject to leakage current, such as subthreshold leakage currents. This may be particularly true at smaller geometry (achievable gate length) transistor sizes, and/or lower power supply voltages. In the event a corresponding transistor of the same discharge path receives a high logic value at its to gate, leakage can be worse.
Referring to FIG. 30, TCAM cell 3002-0 is configured into the empty state, with values X=Y=1. While such a state is desirable in some applications, as it can force a mis-match for the storage location, such a state also enables leakage paths Ileak1 and Ileak2 down both discharge paths N300/N302 and N301/N303. TCAM cell 3002-1 shows an arrangement in which only one stored data value is a logic high. This can still create an undesirable current path down one discharge path in the cell (in the case X=1, resulting in current Ileak3 through discharge path N300/N302). TCAM cell 3002-2 shows a lowest leakage configuration, with the TCAM cell 3002-2 with values X=Y=0.
In some applications, XY TCAM devices can have all entries programmed to an empty state prior to having data values stored within. As a result, when such a TCAM device is sparsely populated (i.e., most entries remain unused), considerable leakage current can be drawn by the large number of empty TCAM cells. In addition, in many conventional XY TCAMs, storage circuits (e.g., 3008-0 and 3008-1) can initialize (e.g., power-up) into unknown or random states. Thus, upon initialization, a TCAM can have many leakage paths through cells like those described above.
Many conventional CAM devices distinguish between “valid” entries and “invalid” entries. Valid entries can store a data value for use in a compare operation. That is, when data of a valid entry indicates a match with a comparand value, a valid match result can be generated. Invalid entries include data that should be excluded from search operations. That is, data of an invalid entry should not indicate a match, regardless of an applied comparand value. Typically, an entry can include one (or a very limited number of) bit location(s) designated as valid bits. Valid bit(s) can be set to a value (e.g., logic “1” or logic “0”) to designate an entry as valid or invalid. In a search operation, a search key can include a corresponding search valid bit(s) for comparison with that of the entry. Valid bits of an invalid entry will not match the search valid bits, and thus force a mis-match for the entry.